There have been many attempts to combine the advantages of large, high quality Si substrates with the superior electronic and optical properties of III/V-compound semiconductors, such as GaAs. Monolithic integration of optoelectronic GaAs devices on Si substrates has been a goal for more than two decades (for a review, see for example Mat. Res. Soc. Symp. Proc. 116 (1989), the content of which is incorporated herein by reference). The 4% lattice mismatch between GaAs and Si induces, however, large defect densities when GaAs is grown epitaxially on Si, leading to greatly degraded properties (see for example Ahrenkiel et al., J. Electrochem. Soc. 137, 996 (1990), the content of which is incorporated herein by reference).
In order to reduce defect densities, various kinds of intermediate buffer layers between the Si substrate and the GaAs layer have been devised. The object of these epitaxial buffer layers is to act as virtual substrates (VS) with a lattice parameter close to that of the GaAs layer.
The lattice parameter of the virtual substrate should thus be larger than that of the Si substrate by about 4%. During epitaxy, a layer normally adapts its lateral lattice parameter to that of the substrate as long as it is sufficiently thin. A buffer layer acting as virtual substrate must therefore be grown beyond the critical thickness for plastic strain relaxation. For strain relaxation to occur, misfit dislocations necessarily have to be present at the substrate/buffer layer interface.
On the other hand, the surface of the buffer layer should be as perfect as possible for the layer to act as a virtual substrate. The most common defects are threading dislocations associated with the process of plastic strain relaxation (see for example Blakeslee, Mat. Res. Soc. Symp. Proc. 148, 217 (1989), the content of which is incorporated herein by reference).
Various ways have been devised to reduce the density of threading dislocations on relaxed buffer layers. One possibility is to use Si1−xGex alloys as buffer layers. This scheme makes use of the miscibility of silicon and germanium over the whole concentration range from x=0 to x=1. Instead of growing an alloy layer with constant composition x, the Ge content is gradually increased from x=0 to some final value x=xƒ. This grading of the Ge content has been shown to result in lower threading dislocation densities because of diminished dislocation interaction (see for example U.S. Pat. No. 5,221,413 to Brasen et al., and Fitzgerald et al., Appl. Phys. Lett. 58, 811 (1991), the content of which is incorporated herein by reference).
Grading rates have to be kept low in order to guarantee low threading dislocation densities, preferably below 10% per micrometer (see for example Li et al., J. Vac. Sci. Technol. B 16, 1610 (1998), the content of which is incorporated herein by reference). Larger grading rates were, however, preferred for virtual substrates grown by a vapor deposition method known as ultra-high vacuum chemical vapor deposition (UHV-CVD), because of very low growth rates at the low substrate temperature used (see for example U.S. Pat. No. 5,659,187 to Legoues et al., the content of which is incorporated herein by reference). The class of vapor deposition methods generally called physical vapor deposition suffers from the additional problem of source depletion, as is evident in molecular beam epitaxy (MBE) where electron beam evaporators need to be refilled regularly (see for example Hackbarth et al., Thin Solid Films 369, 148 (2000) the content of which is incorporated herein by reference).
Virtual substrates made from graded Si1−xGex buffer layers suffer from two main disadvantages: (1) they require many micrometers of epitaxial growth for grading rates low enough to ensure low threading dislocation densities, (2) their surfaces are relatively rough, being characterized by the so-called cross-hatch morphology associated with the relaxation process (see for example Lutz et al., Appl. Phys. Lett. 66, 724 (1995), the content of which is incorporated herein by reference).
Because of the large layer thickness epitaxial growth is very time consuming for most prior art techniques. In CVD, growth rates can be enhanced substantially only by increasing the substrate temperature. This leads, however, to strongly enhanced surface roughness. UHV-CVD grown buffer layers graded to pure Ge have exhibited rms surface roughness of 210 nm when grown on on-axis Si(001) substrates. Trenches on the cross-hatched surface were found to be as deep as 600 nm (see for example U.S. Pat. No. 6,039,803 to Fitzgerald et al., the content of which is incorporated herein by reference). The trenches were shown to be associated with pile-ups of threading dislocations because of increased dislocation interaction. Somewhat smoother surfaces and fewer pile-ups were observed on off-cut Si substrates. The rms roughness reached, however, 50 nm even in this case, with the deepest trenches still exceeding 400 nm (see for example U.S. Pat. No. 6,039,803 to Fitzgerald et al., the content of which is incorporated herein by reference).
In order to improve the surface quality and lower the threading dislocation density, an intermediate chemical-mechanical polishing (CMP) step after grading to x=0.5 was therefore found to be necessary (see for example U.S. Pat. No. 6,107,653 to Fitzgerald, and Currie, et al., Appl. Phys. Lett. 72, 1718 (1998), the contents of which are incorporated herein by reference). With such a procedure, a surface roughness of 24 nm and threading dislocation (TD) density of 2×106 cm−2, sufficiently low for integrating minority carrier III/V devices, could be achieved (see for example Currie et al., Appl. Phys. Lett. 72, 1718 (1998), the content of which is incorporated herein by reference). This TD density was found to be low enough to permit the fabrication of minority carrier devices from GaAs-based material grown on top of such virtual substrates. Examples of such devices are solar cells (see for example Ringel et al., Photovoltaic Energy Conversion, Vol. 1, 612 (2003), the content of which is incorporated herein by reference), and light emitting diodes (see for example V. K. Yang et al., “Monolithic integration of III-V optical interconnects on Si using SiGe virtual substrates”, Journal of Materials Science: Materials in Electronics, vol. 13, no. 13 (July 2002) pp. 377-380, the content of which is incorporated herein by reference), and even laser diodes (see for example M. E. Groenert et al., “Monolithic integration of room-temperature cw GaAs/AlGaAs lasers on Si substrates via relaxed graded GeSi buffer layers”, Journal of Applied Physics, vol. 93, no. 1 (Jan. 1, 2003) pp. 362-367, the content of which is incorporated herein by reference).
A common feature of all CVD processes is their relatively inefficient use of expensive source gases, most of which leave the reactor without being decomposed and incorporated in the growing layer.
The only prior art technique capable of growing thick graded buffer layers in an economical way is a vapor deposition method known as low-energy plasma-enhanced chemical vapor deposition (LEPECVD) (see for example C. Rosenblad et al., Appl. Phys. Lett. 76, 427 (2000), the content of which is incorporated herein by reference). The application of the method to fast Si homoepitaxy and strained-layer SiGe heteroepitaxy has been described in U.S. Pat. No. 6,454,855 to von Känel et al., and in PCT application No. WO 98/58099 to von Känel et al, the contents of which are incorporated herein by reference.
With LEPECVD, also relaxed buffer layers serving as virtual SiGe substrates can be grown at average rates above 5 nm/s (see for example EP 1 315 199 A1 by von Känel, the content of which is incorporated herein by reference). Epitaxial growth at these rates is possible even at substrate temperatures below 600° C. Surfaces are much smoother than those achievable by other prior art techniques, with rms roughness on the order of 3-4 nm after grading to pure Ge. The cross-hatch is still present, however, although with much reduced maximum height variations of approximately 10 nm (see for example von Känel et al., Jap. J. Appl. Phys. 39, 2050 (2000), the content of which is incorporated herein by reference). This is much below the roughness values measured on CVD-grown buffer layers, such that no CMP process is required for the subsequent epitaxy of III/V-semiconductor layers.
GaAs layers have been grown by vapor deposition method known as metal-organic chemical vapor deposition (MOCVD) onto relaxed SiGe buffer layers graded to pure Ge fabricated by LEPECVD. These layers formed the basis for the first strained InGaAs quantum well laser operating at room temperature at 1.04 μm (see for example European Patent Application No. EP 1 513 233 by von Känel et al., and Chriqui et al., El. Lett. 39, 1658 (2003), the content of which is incorporated herein by reference).
One of the main problems of prior art approaches based on graded buffer layers is that the large layer thicknesses involved, together with different thermal expansion coefficients, favour crack formation upon cooling from the growth temperature to room temperature (see for example Yang et al., J. Appl. Phys. 93, 3859 (2003), the content of which is incorporated herein by reference). Crack formation in the virtual substrate itself can be avoided by grading to a final Ge content below x=1, such that the pure Ge cap is under compressive stress at the growth temperature (see for example M. T. Currie, et al., Appl. Phys. Lett. 72, 1718 (1998), the content of which is incorporated herein by reference). This turned out to be disadvantageous, however, for the growth of GaAs based devices with incorporated strained active layer channels, such as InxGa1−xAs. The increased compressive strain imposed on the InGaAs channels by the compressed Ge VS caused these channels to relax by means of misfit dislocations at the GaAs/InGaAs interface. Laser action was therefore obtained in none of these channels, except for the one with the smallest thickness of 5 nm (see for example M. E. Groenert et al., “Improved room-temperature continuous wave GaAs/AlGaAs and InGaAs/GaAs/AlGaAs lasers fabricated on Si substrates via relaxed graded GexSi1−x buffer layers”, Journal of Vacuum Science and Technology, vol. 21, no. 3 (May/June 2003) pp. 1064-1069, the content of which is incorporated herein by reference).
Furthermore, the large layer thickness involved in the graded buffer layer approach clearly remains disadvantageous.
There have been several prior art approaches to the fabrication of thinner buffer layers on Si substrates suitable for the subsequent growth of GaAs. One such approach has been to use an amorphous compliant interlayer to relieve the strain in a strontium titanate layer grown epitaxially on Si (see for example US Pat. No. 2002/0030246 A1 to Eisenbeiser et al., the content of which is incorporated herein by reference).
Another approach involves epitaxially depositing layers of pure Ge onto Si substrates. Using atmospheric pressure CVD to first deposit a Ge base layer at low substrate temperature, and then a second Ge layer at higher temperature, one micrometer thick Ge layers with surprisingly low defect densities could be grown (see for example U.S. Pat. No. 6,537,370 to Hernandez et al., the content of which is incorporated herein by reference). These layers were, however, rough and needed chemical mechanical polishing before being useful as virtual substrates. Moreover, because the grown layers were found to be compressively strained, these layers had to be annealed before chemical-mechanical polishing.
A closely related approach was described by Luan et al., using UHV-CVD at much lower growth rates (see Luan et al., Appl. Phys. Lett. 75, 2909 (1999), the content of which is incorporated herein by reference). In this case, a threading dislocation density of 2.3×107 cm−2 was observed on 1 μm thick Ge films after repeated temperature cycling. A similar, equally slow procedure with low-pressure CVD was shown to result in smooth surfaces, with rms roughness as low as 0.5 nm (see for example Colace et al., Appl. Phys. Lett. 72, 3175 (1998), the content of which is incorporated herein by reference).
Smooth epitaxial Ge films several micrometer in thickness were also grown by molecular beam epitaxy (see for example Sutter et al., Solar Energy Materials and Solar Cells 31, 541 (1994), the content of which is incorporated herein by reference). This method is, however, well known to be slow too, with growth rates not exceeding a few tenths of nm/s.
LEPECVD has also been used to deposit Ge films thicker than 3 micrometers at rates of 3.5 nm/s, exceeding those of all other prior art techniques. Post-growth annealing was found to reduce the dislocation density as for the examples mentioned above (see von Känel et al., Jap. J. Appl. Phys. 39, 2050 (2000), the content of which is incorporated herein by reference). These Ge layers were, however, grown on exactly oriented Si(001) wafers. They would not be suitable as virtual substrates for GaAs because of the problem of anti-phase domain formation. Indeed, in this prior art approach, no proof was given for the suitability of the Ge layers as virtual substrates for GaAs epitaxy. Moreover, the large thickness of the Ge layers would create a problem of crack formation in a GaAs layer grown on top.
Further reduction of the threading dislocation density has been achieved by artificial patterning of the Ge layers (see for example Luan et al., Appl. Phys. Lett. 75, 2909 (1999), the content of which is incorporated herein by reference). This patterning was done by etching the Ge film all the way done to the substrate, thus exposing the Si surface in between the Ge features. For small enough feature sizes of the order of 10 μm threading dislocations can move to the side walls under the action of thermally induced strain during changes of the substrate temperature, such that they effectively vanish (see for example Luan et al., Appl. Phys. Lett. 75, 2909 (1999), the content of which is incorporated herein by reference).